This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 11-181874, filed Jun. 28, 1999, the entire contents of which are incorporated herein by reference.
The present invention relates to a flash memory, especially, to a flash memory, which comprises an error correction circuit and has high reliability, and to a flash memory used for such as NAND type flash memory and NOR type flash memory.
Among the nonvolatile semiconductor memories, the flash memory can electrically erase and rewrite data for a comparatively large unit. Then, the flash memory is applied to the memory of BIOS (basic I/O system) in the computer system, the memory of the communication rule etc. in a portable telephone, and the memory of the image in the digital camera, etc. as substitution of the hard disk drive. Therefore, when only one bit error is occurred in the data memorized in the flash memory, crash of the computer system, disable of communication of a portable telephone and destroy of data will be occurred.
Then, when high reliability is required to the system, to which the flash memory is applied, the following function is provided for the system, which manages the flash memory. That is, the function is a function to write into the flash memory by adding the check data to the information data to be memorized so as to be able to detect and correct error, to read the information data and the check data and check if the error exists in the information data, and to correct the error when there is an error.
However, there are many cases that the methods of the error correction are different for each system, which manages the flash memories. For example, if the check data is different or the data length is different, the following disadvantages will be caused. That is, when the data written by a certain system A is read with another system B, even when there is no error in data, correct data is changed as it is assumed that data has an error, misdetection of error which is not able to be corrected, as a result, the destruction of data in the system will occur.
On the other hand, there is a method of equipping the error correction circuit in the flash memory. This method is valid, since this method performs the error correction in the flash memory without depending on the system.
However, since the error correction circuit is complex and the area of the circuit becomes large, the size of the chip of the flash memory becomes large, as a result, the high cost will be caused. On the other hand, the increase of the area of the circuit is suppressed for example by sharing the data memory circuit for reading and writing in part of the error correction circuit in U.S. Pat. No. 5,933,436.
In the flash memory in recent years, the multi-level memory to memorize the data of one or more bits in one memory cell is appeared. However, in the flash memory of the multi-level memory, when one memory cell destroys, the error is caused in the data of two or more bits (that is, the burst error is caused).
To correct such a burst error efficiently by short check data, though there is a method of the error correction based on the Reed-Solomon code, a complex circuit is required to specify the error, the area of the circuit becomes large, the size of the chip of the flash memory becomes large, and the high cost will be caused. On the other hand, in U.S. Pat. No. 5,621,682 and U.S. Pat. No. 5,719,888, the error correction of the multi-level flash memory is performed by the method of the error correction of each bit, and the data of two or more bits written in one memory cell at the same time is relieved by the plurality of check data.
As mentioned above, though the technology of equipping the error correction circuit in the flash memory exists previously, the following flash memory, which comprises the error correction circuit and considers benefits and convenience on practical use, has not been found. For example,
(1) The flash memory, which has interchange-ability with flash memory, which conventional error correction circuit is not equipped,
(2) The flash memory, which shortens the time required to specify detection and the error in error,
(3) The flash memory, which shortens the time required to generate check data,
(4) The flash memory, which prevents harm by error correction circuit from being generated when failure analysis is performed in the product test etc., and
(5) The flash memory, which prevents harm by circuit of error correction in the memory from being generated, when error correction is performed on application system side of the flash memory.
An object of the present invention is to provide the following flash memories.
(1) The flash memory, which can secure interchangeability with a conventional flash memory, which does not comprise error correction circuit.
(2) The flash memory, which can shorten an appearance read time and can shorten an average read time by shortening the time required to detect an error and to specify the error.
(3) The flash memory, which can shorten an appearance write time by shortening the time required to generate check data.
(4) The flash memory to be able to prevent harm from being generated when failure analysis is performed in the product test etc.
(5) The flash memory, which can correctly perform the error correction even when additional information data is written into the memory cell by the flash memory management system.
(6) The flash memory, which can correctly perform error correction without depending on information data length, and can prevent harm from being generated by the error correction circuit equipped in memory when error correction is performed on application system side.
(7) The flash memory, which can select activation or deactivation of the error correction circuit equipped internally and can easily perform failure analysis.
(8) The flash memory, which can commonly product the product, which operates and does not operate internal error correction circuit and improves the productivity.
(9) The flash memory, which can perform error correction with error correction circuit equipped in flash memory in any cases, is stable and has high reliability, in the system, to which the flash memory, which automatically reads the predetermined data from the memory cell array when the power supply is turned on, is applied.
(10) Multi-level flash memory, in which 2-bits data is written in one memory cell, with comparatively small chip size by equipping the error correction circuit using the BCH code.
(11) The flash memory, in which error correction circuit operates normally at read operation after erase operation.
(12) The flash memory, which can check whether check data is correctly generated by outputting information data read from the memory sector and check data to the external device, and has high reliability.
The first flash memory according to the present invention is characterized by comprising: a memory sector with a plurality of flash memory cells; a command interface, which receives a write data input instruction from an external device to generate a write data input instruction signal, and receives a write instruction from the external device to generate a write instruction signal; a first signal buffer, which receives a write enable signal input from the external device; a control signal generation circuit, which is activated by the write instruction signal to generate a control signal; a data input buffer, which is activated by the write data input instruction signal to receive a write data input from the external device in synchronization with the write enable signal; an error correction circuit, which is activated by the write data input instruction signal to receive the write data in synchronization with the write enable signal, and is activated by the write instruction signal to generate a check data for an error correction in synchronization with the control signal; an address buffer, which receives an address data input from the external device; an address signal generation circuit, which is activated by the write data input instruction signal to generate an address signal in a predetermined order based on the address data in synchronization with the write enable signal, and is activated by the write instruction signal to generate an address signal in a predetermined order in synchronization with the control signal; a plurality of data memory circuits, each of which is provided corresponding to each of the plurality of flash memory cells, and receives an allocated address signal, takes and temporarily memorizes the write data and the check data; and write means to be activated by the write instruction signal, and to write the write data and the check data, which are temporarily memorized in the plurality of data memory circuits in the memory sector.
As a preferable manner of the first flash memory a busy signal output circuit, which outputs a busy signal to the external device according to the write instruction signal.
According to the first flash memory, though the input of the information data to the write circuit is performed in synchronization with signal nWE controlled by the external device, the error correction circuit is operated in synchronization with two control signals. That is, the input of the write data and the output of the check data are synchronized with two signals of external control signal nWE and internal control signal CGCLK, respectively.
As a result, processing to generate the check data for the error correction with the internal error correction circuit and processing to input the check data to the write circuit, etc. can be automatically performed in the flash memory even in the period when the external control signal is not input. Therefore, it is possible to provide the compatible flash memory with the flash memory, to which the conventional error correction circuit is not equipped.
The second flash memory according to the present invention is characterized by comprising: a plurality of memory sectors, each of which has a plurality of flash memory cells; a memory cell array having the plurality of memory sectors; a control signal generation circuit, which generates a control signal; a first signal buffer, which receives a read enable signal input from an external device; an address buffer, which receives an address data input from the external device; an address signal generation circuit, which generates an address signal in a predetermined order in synchronization with the control signal, and generates an address signal in a predetermined order based on the address data in synchronization with the read enable signal; read means to select the memory sectors in the memory cell array based on the address data, and to read data from each of the plurality of flash memory cells of selected memory sectors; a plurality of data memory circuits, each of which is provided for each of the plurality of flash memory cells, temporarily memorizes data read from the plurality of flash memory cells corresponding to selected memory sectors and receives an allocated address signal and outputs the data, which is temporarily memorized, read from the plurality of flash memory cells; a data output buffer, which outputs the data, which is read from the plurality of flash memory cells and output from the plurality of data memory circuits, to the external device in synchronization with the read enable signal; and an error correction circuit, which receives the data, which is read from the plurality of flash memory cells and output from the plurality of data memory circuits, in synchronization with the control signal, judges whether the data output from the data output buffer has an error in synchronization with the read enable signal, and corrects an error if there is the error.
In addition, the preferred manners of the second flash memory may be as following (1) to (4).
(1) A command interface, which receives the status read instruction from the external device to generate a status read instruction signal; and status output means to be activated by the status read instruction signal to output whether there is an error in the data read from the plurality of flash memory cells through the data output buffer are further provided.
(2) The error correction circuit can correct a plurality of data in data read from the plurality of flash memory cells, and the status output means can output the number of errors.
(3) The error correction circuit can correct n data (nxe2x89xa71) in the data read from the plurality of flash memory cells and can detect an existence of (n+1) errors, and the status output means can output whether the error can be corrected.
(4) A busy signal output circuit, which continuously outputs a busy signal to the external device for a period when data is read from the plurality of flash memory cells and the error correction circuit receives data read from the plurality of flash memory cells are further provided.
According to the second flash memory, though the information data from the read circuit is output in synchronization with signal nRE controlled from the external device, the error correction circuit operates in synchronization with two control signals. Specifically, the error correction circuit is synchronized with two signals of external control signal nRE and internal control signal ECCLK.
As a result, processing to generate the check data for the error correction with the internal error correction circuit and processing to read the read data (information data and check data) from the read circuit to the error correction circuit, etc. for the error correction can be automatically performed in the flash memory even in the period when the external control signal is not input. Therefore, it is possible to provide the compatible flash memory with the flash memory, to which the conventional error correction circuit is not equipped.
The third flash memory according to the present invention is characterized by comprising: a plurality of memory sectors, each of which has a plurality of flash memory cells; a memory cell array having the plurality of memory sectors; a command interface, which receives a correction read instruction from an external device to generate a correction read instruction signal; a control signal generation circuit, which is activated by the correction read instruction signal to generate a control signal; a first signal buffer, which receives a read enable signal input from an external device; an address buffer, which receives an address data input from the external device; an address signal generation circuit, which generates an address signal in a predetermined order based on the address data in synchronization with the read enable signal, and is activated by the correction read instruction signal to generate an address signal in a predetermined order in synchronization with the control signal; read means to select the memory sectors in the memory cell array based on the address data, and to read data from each of the plurality of flash memory cells of selected memory sectors; a plurality of data memory circuits, each of which is provided of each of the plurality of flash memory cells, temporarily memorizes a data read from the plurality of flash memory cells corresponding to the selected memory sector, respectively, receives an allocated address signal and outputs the data read from the plurality of flash memory cells, which is temporarily memorized; a data output buffer, which outputs the data, which is read from the plurality of flash memory cells and output from the plurality of data memory circuits, to the external device in synchronization with the read enable signal; and an error correction circuit, which receives the data, which is read from the plurality of flash memory cells and output from the plurality of data memory circuits, in synchronization with the read enable signal, receives the data, which is read from the plurality of flash memory cells and output from the plurality of data memory circuits, in synchronization with the control signal, judges whether there is an error in the data read from the plurality of flash memory cells, and specifies the data when there is an error.
In addition, the preferred manners of the third flash memory may be as following (1) to (4).
(1) The command interface receives a status read instruction signal to generate a status read instruction xe2x80x9c70xe2x80x9dH from the external device; and status output means to output whether there is an error in the data which is activated by the status read instruction signal and read from the plurality of flash memory cells, through the data output buffer.
(2) The error correction circuit can correct a plurality of data in data read from the plurality of flash memory cells, and the status output means can output the number of errors.
(3) The error correction circuit can correct n data (nxe2x89xa71) in the data read from the plurality of flash memory cells and can detect an existence of (n+1) errors, and the status output means can output whether the error can be corrected.
(4) A busy signal output circuit, which outputs a busy signal to the external device for reading period of data from the plurality of flash memory cells, and outputs the busy signal to the external device and according to the correction read instruction signal is further provided.
According to the third flash memory, the error correction circuit synchronously operates with two control signals. Specifically, the error correction circuit is synchronized with two signals of external control signal nRE and internal control signal ECCLK. As a result, processing to generate the check data for the error correction with the internal error correction circuit and specify the data when the error exists, etc. can be automatically performed in the flash memory even in the period when the external control signal is not input. Therefore, it is possible to provide the compatible flash memory with the flash memory, to which the conventional error correction circuit is not equipped.
The fourth flash memory according to the present invention is characterized by comprising: a memory sector with a plurality of flash memory cells; a command interface, which receives a write data input instruction from an external device to generate a write data input instruction signal, and receives a write instruction from the external device to generate a write instruction signal; a first signal buffer, which receives a write enable signal input from the external device; a control signal generation circuit, which is activated by the write instruction signal to generate a control signal; a data input buffer, which is activated by the write data input instruction signal to receive a write data input from the external device in synchronization with the write enable signal; an error correction circuit, which is activated by the write data input instruction signal to receive the write data in synchronization with the write enable signal, and is activated by the write instruction signal to generate a check data for an error correction in synchronization with the control signal; a plurality of data memory circuits, each of which is provided for each of the plurality of flash memory cells, and takes the write data and the check data in synchronization with the write enable signal and the control signal to memorize it temporarily; and means to be activated by the write instruction signal, and to write the write data and the check data, which are temporarily memorized in the plurality of data memory circuits in the memory sector.
As a preferable manner of the fourth flash memory, a busy signal output circuit, which outputs a busy signal to the external device according to the write instruction signal is further provided.
According to the fourth flash memory, though it is different that the write data or the check data are taken in synchronization with external control signal nWE and internal control signal CGCLK, but not with the allocated address signal, when the write data or the check data is taken and is temporarily memorized into data memory circuit, compared with the first flash memory, an advantage basically similar to the first flash memory can be achieved.
The fifth flash memory according to the present invention is characterized by comprising: a plurality of memory sectors, each of which has a plurality of flash memory cells; a memory cell array having the plurality of memory sectors; a control signal generation circuit, which generates a control signal; a first signal buffer, which receives a read enable signal input from an external device; an address buffer, which receives an address data input from the external device; read means to select the memory sectors in the memory cell array based on the address data, and to read data from each of the plurality of flash memory cells of selected memory sectors; a plurality of data memory circuits, each of which is provided for each of the plurality of flash memory cells, and temporarily memorizes the data read from the plurality of flash memory cells corresponding to the selected memory sector, and outputs the data read from the plurality of flash memory cells, which are temporarily memorized in synchronization with the control signal and the read enable signal; a data output buffer, which outputs the data, which is read from the plurality of flash memory cells and output from the plurality of data memory circuits to the external device in synchronization with the read enable signal; and an error correction circuit, which receives the data, which is read from the plurality of flash memory cells and output from the plurality of data memory circuits, in synchronization with the control signal, judges whether the data output from the data output buffer has an error in synchronization with the read enable signal, and corrects the error if there is an error.
In addition, the preferred manners of the fifth flash memory may be as following (1) to (4).
(1) A command interface, which receives the status read instruction from the external device to generate a status read instruction signal; and status output means to be activated by the status read instruction signal to output whether there is an error in the data read from the plurality of flash memory cells through the data output buffer are further provided.
(2) The error correction circuit can correct a plurality of data in data read from the plurality of flash memory cells, and the status output means can output the number of errors.
(3) The error correction circuit can correct n data (nxe2x89xa71) in the data read from the plurality of flash memory cells and can detect an existence of (n+1) errors, and the status output means can output whether the error can be corrected.
(4) A busy signal output circuit, which continuously outputs a busy signal to the external device for a period when data is read from the plurality of flash memory cells and the error correction circuit receives data read from the plurality of flash memory cells is further provided
According to the fifth flash memory, though it is different that the data is synchronized with internal control signal ECCLK and external control signal nRE, but not with the allocated address signal, when the data is output from data memory circuit, compared with the second flash memory, an advantage basically similar to the second flash memory can be achieved.
The sixth flash memory according to the present invention is characterized by comprising: a plurality of memory sectors, each of which has a plurality of flash memory cells; a memory cell array having the plurality of memory sectors; a command interface, which receives a correction read instruction from an external device to generate a correction read instruction signal; a control signal generation circuit, which is activated by the correction read instruction signal to generate a control signal; a first signal buffer, which receives a read enable signal input from an external device; an address buffer, which receives an address data input from the external device; read means to select the memory sectors in the memory cell array based on the address data, and to read data from each of the plurality of flash memory cells of selected memory sectors; a plurality of data memory circuits, each of which is provided for each of the plurality of flash memory cells, and temporarily memorizes the data read from the plurality of flash memory cells corresponding to the selected memory sector and outputs the data read from the plurality of flash memory cells which has been temporarily memorized in synchronization with the read enable signal and the control signal; a data output buffer, which outputs the data, which is read from the plurality of flash memory cells and output from the plurality of data memory circuits, to the external device in synchronization with the read enable signal; and an error correction circuit, which receives the data, which is read from the plurality of flash memory cells and output from the plurality of data memory circuits, in synchronization with the read enable signal, receives the data, which is read from the plurality of flash memory cells and output from the plurality of data memory circuits, in synchronization with the control signal, judges whether there is an error in the data read from the plurality of flash memory cells, and specifies the data when there is an error.
In addition, the preferred manners of the sixth flash memory may be as following (1) to (4).
(1) The command interface receives a status read instruction signal to generate a status read instruction xe2x80x9c70xe2x80x9dH from the external device; and status output means to output whether there is an error in the data which is activated by the status read instruction signal and read from the plurality of flash memory cells, through the data output buffer.
(2) The error correction circuit can correct a plurality of data in data read from the plurality of flash memory cells, and the status output means can output the number of errors.
(3) The error correction circuit can correct n data (nxe2x89xa71) in the data read from the plurality of flash memory cells and can detect an existence of (n+1) errors, and the status output means can output whether the error can be corrected.
(4) A busy signal output circuit, which outputs a busy signal to the external device for reading period of data from the plurality of flash memory cells, and outputs the busy signal to the external device and according to the correction read instruction signal is further provided.
According to the sixth flash memory, though it is different that the data is synchronized with external control signal nRE and internal control signal ECCLK, but not with the allocated address signal, when the data is output from data memory circuit, compared with the third flash memory, an advantage basically similar to the third flash memory can be achieved.
The seventh flash memory according to the present invention is characterized by comprising: a memory sector with a plurality of flash memory cells; a signal buffer, which receives a write enable signal input from an external device, and outputs a first control signal in a first period; a control signal generation circuit, which generates a second control signal in a second period different from the first period; a data input buffer, which receives a write data input from the external device in synchronization with the write enable signal; an error correction circuit, which receives the write data in synchronization with the first control signal to generate a check data for an error correction in synchronization with the second control signal; a plurality of data memory circuits, each of which is provided for each of the plurality of flash memory cells, and takes the write data and the check data in synchronization with the first control signal and the second control signal and memorizes it temporarily; means to write the write data and the check data, which are temporarily memorized in the plurality of data memory circuits, in the memory sector.
As a preferable manner of the seventh flash memory, a busy signal output circuit, which outputs busy signal to the external device in the second the period is further provided.
According to the seventh flash memory, though it is different that two internal control signals CGCLK and INCLK are used, compared with the first flash memory, an advantage basically similar to the first flash memory can be achieved.
The eighth flash memory according to the present invention is characterized by comprising: a plurality of memory sectors, each of which has a plurality of flash memory cells; a memory cell array having the plurality of memory sectors; a control signal generation circuit, which generates a first control signal in a first period; signal buffer, which receives a read enable signal input from an external device, and outputs a second control signal in a second period different from the first period; an address buffer, which receives an address data input from the external device; read means to select the memory sectors in the memory cell array based on the address data, and to read data from each of the plurality of flash memory cells of selected memory sectors; a plurality of data memory circuits, each of which is provided for each of the plurality of flash memory cells, and temporarily memorizes the data read from the plurality of flash memory cells corresponding to the selected memory sector and outputs the data read from the memory cell, which temporarily memorizes it, in synchronization with the first control signal and the second control signal; a data output buffer, which outputs the data, which is read from the plurality of flash memory cells and output from the plurality of data memory circuits, to the external device in synchronization with the second the signal; an error correction circuit, which receives the data, which is read from the plurality of flash memory cells and output from the plurality of data memory circuits, in synchronization with the first control signal, judges whether the data output from the data output buffer has an error in synchronization with the second the signal, and corrects the error if there is an error.
In addition, the preferred manners of the eighth flash memory may be as following (1) to (4).
(1) A command interface, which receives the status read instruction from the external device to generate a status read instruction signal; and status output means to be activated by the status read instruction signal to output whether there is an error in the data read from the plurality of flash memory cells through the data output buffer are further provided.
(2) The error correction circuit can correct a plurality of data in data read from the plurality of flash memory cells, and the status output means can output the number of errors.
(3) The error correction circuit can correct n data (nxe2x89xa71) in the data read from the plurality of flash memory cells and can detect an existence of (n+1) errors, and the status output means can output whether the error can be corrected.
(4) A busy signal output circuit, which continuously outputs a busy signal to the external device for a period when data is read from the plurality of flash memory cells and the error correction circuit receives data read from the plurality of flash memory cells is further provided
According to the eighth flash memory, though it is different that two internal control signals ECCLK and OUTCLK are used, compared with the second flash memory, an advantage basically similar to the second flash memory can be achieved.
The ninth flash memory according to the present invention is characterized by comprising: a plurality of memory sectors, each of which has a plurality of flash memory cells; a memory cell array having the plurality of memory sectors; a signal buffer, which receives a read enable signal input from an external device, and outputs a first control signal in a first period; a control signal generation circuit, which generates a second control signal in a second period different from the first period; an address buffer, which receives the address data input from the external device; read means to select the memory sectors in the memory cell array based on the address data, and to read data from each of the plurality of flash memory cells of selected memory sectors; a plurality of data memory circuits, each of which is provided for each of the plurality of flash memory cells, temporarily memorizes the data read from the plurality of flash memory cells corresponding to the selected memory sector and outputs the data read from the memory cell, which temporarily memorizes it, in synchronization with the first control signal and the second control signal; a data output buffer, which outputs the data, which is read from the plurality of flash memory cells and output from the plurality of data memory circuits, to the external device in synchronization with the first control signal; and an error correction circuit, which receives the data, which is read from the plurality of flash memory cells and output from the plurality of data memory circuits, in synchronization with the first control signal, receives the data, which is read from the plurality of flash memory cells and output from the plurality of data memory circuits, in synchronization with the second control signal, judges whether there is an error in the data read from the plurality of flash memory cells, and specifies the data when there is an error.
In addition, the preferred manners of the ninth flash memory may be as following (1) to (4).
(1) A command interface, which receives the status read instruction from the external device to generate a status read instruction signal; and status output means to be activated by the status read instruction signal to output whether there is an error in the data read from the plurality of flash memory cells through the data output buffer are further provided.
(2) The error correction circuit can correct a plurality of data in data read from the plurality of flash memory cells, and the status output means can output the number of errors.
(3) The error correction circuit can correct n data (nxe2x89xa71) in the data read from the plurality of flash memory cells and can detect an existence of (n+1) errors, and the status output means can output whether the error can be corrected.
(4) A busy signal output circuit which outputs busy signal to the external device in a read period of data from the memory cell, and outputs a busy signal to the external device in the second period is further provided.
According to the ninth flash memory, though it is different that two internal control signals ECCLK and OUTCLK are used, compared with the third flash memory, an advantage basically similar to the third flash memory can be achieved.
As mentioned above, the error correction circuit is operated in synchronization with two control signals in the first to ninth flash memory according to the present invention. That is, by synchronizing the operation of the error correction circuit with the external control signal and the internal control signal, processings such as processing to generate the check data for the error correction with the internal error correction circuit, processing to input the check data to the write circuit, and processing to read the read data (information data and check data) to the error correction circuit from the read circuit for the error correction can be automatically processed internally, even in the period when the external control signal is not input. Therefore, it is possible to provide the compatible flash memory with the flash memory, to which the conventional error correction circuit is not equipped.
The tenth flash memory according to the present invention is characterized by comprising: a memory sector with a plurality of flash memory cells; a busy signal output circuit, which outputs busy signal to the external device; a data input buffer, which receives the write data written in each memory cell input from the external device; a plurality of data memory circuits which can memorize n bits to temporarily memorize the write data; and an error correction circuit, which takes m1-bits write data (m1 less than n) to generates m2-bits check data, and takes m3 bits write data (m1+m2+m3 less than n) to generate m4 bits check data (m1+m2+m3+m4xe2x89xa7n) after generating m2-bits check data (m1+m2xe2x89xa7n), wherein the m2-bits check data is input to the plurality of data memory circuits after the m1-bits write data is input to the plurality of data memory circuits to be memorized temporarily, the m4 bits check data is input to the plurality of data memory circuits after the m3 bits write data is input to the plurality of data memory circuits to be memorized temporarily, and the m1 and m3 bits write data and m2 and the m4 bits check data, which are temporarily memorized in the plurality of data memory circuits, are written in the memory sector after the m4 bits check data is temporarily memorized in the plurality of data memory circuits.
According to the tenth flash memory, the information data for two memory sectors is received, and is written in two memory sectors in a lump. The busy signal is given when the information data written in the first memory sector is input, and the check data is generated internally such that the flash management system recognizes that the flash memory is in a write operation. As a result, since the check data can be generated in a short time compared with writing, the flash memory, in which an appearance write time is short, can be provided.
The eleventh flash memory according to the present invention is characterized by comprising: a memory sector with a plurality of flash memory cells; a busy signal output circuit, which outputs busy signal to the external device; an error correction circuit, which reads the read data from the memory sector and specifies the error read data, wherein a busy signal is continuously output from the busy signal output circuit to the external device from a period when the read data from the memory sector to a period when the error correction circuit specifies a error read data.
According to the eleventh flash memory, busy signal nBUSY is continuously output to the external device in the period of reading data from the memory sector and specifying the error with error correction circuit. Therefore, it is possible to provide the compatible flash memory with the flash memory, to which the conventional error correction circuit is not equipped.
The twelfth flash memory according to the present invention is characterized by comprising: a memory sector with a plurality of flash memory cells; a data buffer, which outputs a read data read from the memory sector to an external device; an error correction circuit, which output the read data from the data buffer and inputs the read data to specify an error read data from the read data, characterized in that when the read data is output from the data buffer to the external device again, the error correction circuit corrects the error read data.
In addition, the preferred manners of the twelfth flash memory may be as following (1) to (2).
(1) A status output circuit which outputs an error state to the external device is further provided.
(2) A plurality of data memory circuits, which temporarily memorize to read data read from the memory sector are further provided.
According to the twelfth flash memory, the error correction circuit is operated while outputting the read data to the external device. Thereafter, the error correction processing of the remainder data is performed, and only when there is an error, the error correction is performed again and data is output to the external device.
Therefore, it is possible to provide the flash memory, which can shorten the time required to detect the error from the read data with the internal error correction circuit and to specify the error and the appearance read time, and has the short average read time.
The thirteenth flash memory according to the present invention is characterized by comprising: a memory sector to which has a plurality of the plurality of flash memory cells; means to write an information data and a check data in the memory sector; means to read the information data and the check data from the memory sector; and an error correction circuit, which generates the check data from the information data and performs an error correction of the information data based on the information data and the check data, wherein the error correction circuit generates the check data by replacing the information data read from at least one predetermined memory cell with a predetermined dummy data, and corrects the information data by replacing the information data read from the predetermined memory cell with the dummy data.
According to the thirteenth flash memory, the information data written in the predetermined memory cell is replaced with fixed data, the check data is generated, and the error correction is performed.
Accordingly, the flash memory, which can correctly perform the error correction even when the flash memory management system writes the additional information data in the memory cell, can be provided.
The fourteenth flash memory according to the present invention is characterized by comprising: a memory sector to which has a plurality of the plurality of flash memory cells; means to write the predetermined n bits information data and a check data in the memory sector; means to read the n bits information data and the check data from the memory sector; and an error correction circuit, which generates the check data from the n bits information data and performs an error correction of the n bits information data from the n bits information data and the check data, wherein the error correction circuit effectively adds a predetermined (nxe2x88x92m) bits dummy data as information data when the information data input from the external device is m bits (m less than n), and generates the check data.
According to the fourteenth flash memory, the error correction can be correctly performed even when the information data length input from the external device is not predetermined length. That is, the error correction can be correctly performed even when the information data length from the flash memory management system is shorter than the predetermined length. Therefore, it is possible to provide the flash memory, which can correctly perform the error correction not to depend on the information data length.
The fifteenth flash memory according to the present invention is characterized by comprising: a memory sector to which has a plurality of the plurality of flash memory cells; means to write an information data and a check data in the memory sector; means to read the information data and the check data from the memory sector; an error correction circuit, which generates the check data from the information data, and performs an error correction of the information data from the information data and the check data; and a switch circuit, which selects whether the information data is output to the external device by performing the error correction or the information data is output to the external device without the error correction.
According to the fifteenth flash memory, it is possible to select activation or deactivation of the error correction circuit equipped internally by equipping an electric switch. Therefore, it is possible to provide the flash memory, in which failure analysis can be easily performed.
That is, when the error correction circuit is always activated and corrects error and output data, though there is a disadvantage of difficulty of failure analysis in the product test, when it is unclear whether error is occurred, or which memory cell causes the error, the above-mentioned disadvantage can be prevented from being generated by providing the selection circuit.
Thus, by selecting activation or deactivation the error correction circuit equipped internally, it is possible to provide flash memory in which a failure analysis can be easily performed.
The sixteenth flash memory according to the present invention is characterized by comprising: a memory sector to which has a plurality of the plurality of flash memory cells; means to write an information data and a check data in the memory sector; means to read the information data and the check data from the memory sector; an error correction circuit, which generates the check data from the information data, and performs an error correction of the information data from the information data and the check data; and a switch circuit, which selects whether the error correction circuit is activated or deactivated.
According to the sixteenth flash memory, it is possible to select activation or deactivation of the error correction circuit equipped internally by equipping the switch which can be fixed when the product is shipped. Therefore, it is possible to provide the flash memory, in which it becomes possible to commonly produce the product, which operates the internal error correction circuit and the product, which does not operate it.
That is, when the error correction is performed in the system to which the flash memory is applied, only since the internal error correction operation slows writing and the read operations, it is necessary to deactivate the internal error correction circuit. Disadvantage of lowering productivity to divide the product which operates the internal error correction circuit and the product which does not operate it, can be solved by equipping the selection circuit.
The seventeenth flash memory according to the present invention is characterized by comprising: a plurality of memory sectors, each of which has a plurality of flash memory cells; a memory cell array having the plurality of memory sectors; means to write an information data and a check data in the memory sector; means to read the information data and the check data from the memory sector; an error correction circuit, which generates the check data from the information data, and performs an error correction of the information data from the information data and the check data; and means to read data of a predetermined memory sector according to a turn-on of a power supply.
According to the seventeenth flash memory, it is possible to provide the flash memory, in which the error correction becomes possible with the error correction circuit equipped in the flash memory in any cases, being stable and having high reliability, in the system, to which the flash memory, which automatically reads the predetermined data from the memory cell array with the power supply being turned on, is applied.
That is, in the system, which uses the flash memory, which automatically reads the predetermined data from the memory cell array with the power supply being turned on, when it is assumed to control the flash memory according to the predetermined data, it can be possible to solve the disadvantage that, when this system performs the error correction, error correction is not effective since it is previous to being turned on the system concerning the predetermined data.
The eighteenth flash memory according to the present invention is characterized by comprising: a memory sector to which has a plurality of the plurality of flash memory cells; multi-level write means to write a first information data and a first check data in each of the plurality of flash memory cells of the memory sector per one bit, thereafter, further write one bit in each of the plurality of flash memory cells of the memory sector based on the written first information data, the written first check data, a second information data and second check, to write two-bits data in one memory cell; multi-level read means to read the first information data and the first check data from the memory sector, and to read the second information data and the second check data from the memory sector; and an error correction circuit, which generates the first check data from the first information data, generates the second check data from the second information data, corrects an error in the first information data from the first information data and the first check data, and corrects an error in the second information data from the second information data and the second check data, wherein the error correction circuit performs a generation and an error correction of the check data based on a BCH code.
According to the eighteenth flash memory, the first information data and the first check data are written in each memory cell of the memory sector in one bit, thereafter, from the written first information data, the written first check data, the second information data and the second check data, further one-bit is written in each memory cell of the memory sector, and the two-bits data is written in one memory cell. The circuit based on the BCH code is equipped. Therefore, the multi-level flash memory with comparatively small chip size can be provided.
That is, error of two or more bits is caused by destroying one memory cell in the multi-level flash memory. Therefore, the method, which the burst error can be corrected, is efficient as the method of the error correction. On the other hand, the error correction circuit for the bit unit is comparatively easy, and is a little the increase of the size of the chip. The disadvantage that the relief efficiency is low when the error correction circuit, which corrects the error by the bit unit, is applied as an error correction circuit applied to a multi-level flash memory, can be solved.
The nineteenth flash memory according to the present invention is characterized by comprising: a memory sector to which has a plurality of the plurality of flash memory cells; an erase circuit which erases the memory sector, and sets data of all memory cells to xe2x80x9c1xe2x80x9d; means to write an information data and a check data in the memory sector; means to read the information data and the check data from the memory sector; and an error correction circuit, which generates the check data from the information data, and performs an error correction of the information data from the information data and the check data, wherein the error correction circuit generates the check data of all xe2x80x9c1xe2x80x9d from the information data of all xe2x80x9c1xe2x80x9d.
According to the nineteenth flash memory, the data of the memory cell, which is erased, is set to be xe2x80x9c0xe2x80x9d. The error correction circuit is set so that all the entire check data of xe2x80x9c0xe2x80x9d is generated for the information data of xe2x80x9c0xe2x80x9d. Therefore, it is possible to provide the flash memory, in which the error correction circuit operates normally in read operation after erasure.
That is, there is a case that data is often read after the data of the flash memory, which equips the error correction circuit, is erases. The disadvantage of mis-detection, of which the error exists, when the error correction circuit operates in this case, can be solved.
The twentieth flash memory according to the present invention is characterized by comprising: a memory sector with a plurality of flash memory cells; an error correction circuit, which generates a check data for the error correction from an information data input from an external device, and performs an error correction of the information data from the information data and the check data; a plurality of data memory circuits each of which is provided to each of the plurality of flash memory cells; means to write the information data and the check data, which are temporarily memorized in the plurality of data memory circuits, in the memory sector; means to read the information data and the check data from the memory sector to the plurality of data memory circuits; and means to output the information data and the check data, which is memorized in the plurality of data memory circuits, read from a memory sector to the external device.
According to the twentieth flash memory, means to output the information data and the check data read from the memory sector to the external device is comprised. Therefore, it is possible to provide the flash memory, which can checks whether the check data can be correctly generated, and has high reliability.
The twenty-first flash memory according to the present invention is characterized by comprising: a memory sector with a plurality of flash memory cells; an error correction circuit, which generates a check data for the error correction from an information data input from an external device, and performs an error correction of the information data from the information data and the check data; a plurality of data memory circuits each of which is provided to each of the plurality of flash memory cells; means to write the information data and the check data, which are temporarily memorized in the plurality of data memory circuits, in the memory sector; and means to read the information data and the check data from the memory sector to the plurality of data memory circuits, wherein the data memorized in the plurality of data memory circuits is reset to data predetermined xe2x80x9c1xe2x80x9d before inputting the information data from the external device.
According to the twenty-first flash memory, the information data written in the predetermined memory cell is replaced with fixed data and the check data is generated, in error correction circuit. In this case, the information data and the check data are temporarily memorized in a plurality of data memory circuits, which are provided to each memory cell, and are written in the memory cell in a lump. In the data memory circuit, the memorized data is reset to fixed data before inputting the information data. Therefore, the flash memory, which has a simple and fast circuit and can correctly perform the error correction without depending on the data length, can be provided.
The present invention is not limited to the following embodiment. The flash memory cell is not limited to the NAND type memory cell, and may include the memory cell such as the NOR type memory cells and virtual ground memory cell. The sizes of the cluster is four sectors in the embodiment as mentioned above, but it is possible to choose according to the characteristic of the system like 8 sectors, 9 sectors, and 16 sectors, etc. The number of the clusters may be the same as the number of the sectors.
Additional objects and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed out hereinafter.